This invention relates to the field of integrated circuit (IC) design. Specifically, it relates to dynamic delays for data transfers for a high-speed synchronous embedded semiconductor memory system having a micro-cell architecture.
Memory performance has improved with the evolution from single data rate (SDR) to double data rate (DDR) dynamic random access memory (DRAM); the latter incorporating synchronization of internal timing signals with an external or system clock. The cycle time for synchronized DDR memory is typically 6.6 ns. Reduction of the cycle time below 4 ns, has been found to be extremely difficult to accomplish. Data bandwidth and system demand have continued to increase with the use of high-performance embedded DRAM (eDRAM), causing the need for reliable data transferring and a cycle time under 2 ns.
EDRAMs with wide data bandwidth and wide internal bus width have been proposed to be used as L2 (Level-2) cache to replace pure SRAM cache. Since each DRAM memory cell is formed by a transistor and a capacitor, the size of DRAM cache is significantly smaller than that of SRAM cache. In order to meet performance requirements, an eDRAM is formed of a plurality of blocks or micro-cells arranged in arrays forming one or more banks. A block is a small DRAM array unit formed by a plurality of wordlines (e.g., from 64 to 256) and a plurality of bitline pairs (e.g., from 64 to 256). The size of a block is much smaller (e.g., 16xc3x97 to 256xc3x97) than that of a bank of a conventional stand-alone DRAM. Typically one block of each eDRAM bank is activated at a time. It is possible for blocks from different banks to be accessed simultaneously for simultaneous read and write operations. The read and write speed of an eDRAM can be fast due to very light loading of wordlines and bitlines.
An SRAM array of SRAM macros is provided for effectively utilizing the large eDRAM cache size. The SRAM array, similar in size to an eDRAM block, is provided for serving as a cache interface in-between the eDRAM bank(s) and one or more processors and for facilitating a high-speed pipeline operation in the eDRAM.
During high-speed data transfers it is important to preserve data integrity. Timing related problems such as data collision along a data path and mismatching of data and data addresses compromise data integrity. Thus, proper timing of data transfers affects data reliability.
One approach for providing a timing system for high-speed data transfers is to provide a distributed data clock for coordinating flow of data. However, the distributed data clock occupies additional valuable chip space. Even though this approach is practical for DRAMs having an array size of 16M and below, in an array size larger than 16M, a data-latching window for data located near the SRAM array interface would be shrunk too small to be acceptable for a reliable read/write operation.
To overcome this problem associated with the approach, it would be ideal to distribute the data, the associated address bits and control signals to each bank of the memory for providing a steady relative timing among the data, clock, address bits and control signals, etc. The resulting data-latching window would not be compromised regardless of the location of the data is being sent to or read from. Overlapping of read and write data pulses would be avoided. However, this solution would require approximately a two-fold increase of the size of the circuitry associated with the data paths. Hence, array efficiency would be significantly reduced and the chip size would be increased.
Accordingly, a need exists for a timing system in a high speed semiconductor memory system providing reliable high-speed data transfers without increasing the size of the semiconductor memory system. Furthermore, a need exists for a timing system in a high-speed semiconductor memory system in which data is transferred reliably at a high speed regardless of the location of the data being transferred, without increasing the size of the semiconductor memory system. Furthermore, a need exists for a method and system for providing a steady timing for data transfers within a high-speed semiconductor memory system, regardless of the location of the data being transferred, without increasing the size of the semiconductor memory.
An aspect of the present invention is to provide a timing system in a compact semiconductor memory system in which data is transferred reliably at high speeds.
Another aspect of the present invention is to provide a timing system in a compact semiconductor memory system in which data is transferred at high speeds, and in which the reliability of the data transfer is independent of the location of the data being transferred.
Another aspect of the present invention is to provide a method and system for providing high-speed data transfers within a high performance semiconductor memory system, in which a steady latch window is provided for each data transfer, regardless of the location of the data being transferred.
Accordingly, a timing system for controlling timing of data transfers within memory system is provided. The timing system includes a programming circuit for generating a bias signal, wherein the bias signal is biased in accordance with an incoming data transfer address corresponding to a memory address of the memory system, and a delay module for receiving the bias signal and generating an output clock signal, wherein the output clock signal is delayed in accordance with the bias signal and therefore data address.
Furthermore, a method for controlling timing of data transfers within a memory system is provided including the steps of receiving an incoming address of a memory cell of the memory system transferring data; processing the incoming address; generating a bias signal in accordance with the processed incoming address; generating a clock output signal having a delay in accordance with the bias signal; and controlling release of data held in a control region of the eDRAM system during a data transfer via the clock output signal.